Embodiments of the invention described herein relate to cache memory access.
Virtually any computing system or digital processing system relies on memory to function. Processing may generally be accelerated by speeding up access to memory. A memory cache may be used to achieve this. In the area of computer graphics, cache memory may be used in support of the rendering process, where fast processing of large amounts of data is required. Cache memory in this or any other application typically allows reads and writes by more than one client. Given frequent repeated access by clients, the cache memory device may be built with multiple read and write ports.
This comes at significant cost, however. Multiple read or write ports represent additional gates. Tens of thousands of additional gates may be necessary to implement additional read and write ports. Additional gates may in turn dictate that the cache memory device be physically larger than it would otherwise be, as well as more expensive. Additional gates may also increase power requirements and create heat dissipation problems.